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Early Integration Gains Steam

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By Ed Sperling
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort lately has been targeted toward better and earlier integration of new or enhanced tools and toward combining IP blocks into subsystems.

To some extent this is simply good housekeeping—roughly EDA’s equivalent of making software backward compatible. Ensuring that that tools work with each other in a flow that now has to be concerned with hardware, software, power, electromigration, standards—and all the while making this work across a globally disaggregated supply chain—is an incredibly complex management challenge. But there is also at least an early indication, and one that apparently warrants big investments on the part of EDA vendors, hat at 28nm and beyond many of their customers’ in-house tools are running out of steam. Even better for EDA, there is far less money being appropriated to develop new internal tools.

This explains the rising clamor by customers for more standards. Chipmakers certainly don’t want to pay top dollar for EDA tools, and standards make it easier to chop costs—or at least to negotiate a deal. That’s partly what’s behind the increasing amount of noise about existing standards such as the dueling power formats, CPF and UPF/1801. It also explains why there is more collaboration under way between chipmakers and EDA vendors to develop complex solutions, because while chipmakers may experience a limited number of problems, EDA vendors deal with a much greater universe of the same or related issues and draw from a larger pool of chipmakers to offer advice.

All of the big EDA vendors recognize these changes, and their recent product releases clearly reflect it. Witness Cadence’s announcement today of tighter integration between its System Development Suite, with in-circuit acceleration, and its VIP catalog, which now has hooks for both acceleration and emulation. What that means, in a nutshell, is that simulation and emulation teams now can share a verification environment, and the VIP catalog is now compatible with the Accellera Co-Emulation and Modeling Interface (SCE-MI) standard.

“The goal is to push use models from NRE to automation,” said Michal Siwinski, group director for product marketing for Cadence’s System and Software Realization Group. “There are two elements to this. One is in-circuit acceleration to the System Development Suite. The second is a VIP catalog that has been expanded for acceleration and emulation.”

Both Mentor Graphics and Synopsys have been taking similar steps for their respective environments. Mentor, for instance, has been active in bridging a variety of its embedded software tools into a standard flow, and in making emulation far more attractive for software developers by adding a desktop virtualization layer. The company also has been working heavily on making it easier for chipmakers to develop and incorporate embedded software into their designs.

Synopsys has been integrating a number of pieces in other areas, most recently in the 2.5D/3D IC world where it has begun integrating test, IP, parasitic extraction, simulation, DFM and thermo-mechanical stress analysis into the same flow. It also has been working hard to integrate hardware and software.

“The interaction of components is much more important,” said Alan Gibbons, principal engineer at Synopsys. “A lot of this is not being modeled today, and if it is it’s happening on a spreadsheet. We need more intelligent algorithms to make this work.”

Along the same lines, but in different market, Cadence has launched an NVM Express memory subsystem for enterprise computing environments. “This will dramatically reduce the time it takes to integrate and optimize,” said Neil Hand, group production marketing director for Cadence’s SoC Realization Group. “NVMe was built on PCI Express. This is a natural move to a subsystem and it leverages a lot of expertise in storage and high-performance interfaces.”

This follows on the heels of similar moves by Synopsys in the audio subsystem arena (as well as its NVM Express VIP), and by companies such as Tensilica in the audio and video subsystem world.

Simon Butler, CEO of Methodics, said the move from IP to subsystems eliminates a lot of the “grunt work” by bundling in firmware and development tools.

“There’s a lot of history behind using the appropriate infrastructure with functional blocks,” said Butler. “The challenge is in trying to accommodate both of those. Generally speaking, the larger the block the more you need to remove the complexity, and the way you do that is to give it to the IP vendors and let them do it.”

Butler said that characterizing subsystems rather than just IP blocks is a big step forward. “The fact that programming and interacting can be done at a higher level means the use model is easier. How perfectly it behaves electrically is driven by the application. But if you see enough traffic going through a subsystem, you bring more to the table and are able to solve more problems. So basically your integration work as a customer is going down because the vendor is supplying the abstraction layer.”

With all of the big three EDA vendors on board, this focus on integration will likely establish the theme for the upcoming Design Automation Conference in San Francisco early next month. The big questions now are what else will be integrated, and by whom.


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